1. Technical Field
The present invention generally relates to supercomputing systems. More specifically, the present invention relates to supercomputing architectures and methods for operating supercomputing architectures.
2. Description of the Related Art
Existing supercomputing architectures include multiple layers of communication in transferring data to and/or from disk storage, archival storage, supporting servers, and/or networks. Multiple hardware components and computer systems are used in implementing these multiple layers of communication, as shown in FIG. 1 which illustrates an exemplary prior art supercomputing system.
As shown, a prior art supercomputing system 100 includes compute nodes (comp nodes) 110A1-110AN (for some non-zero natural number N) coupled to high performance computing (HPC) switches 115A1-115AM (for some non-zero natural number M) coupled to input/output (I/O) nodes 120A1-120AL (for some non-zero natural number L) coupled to Internet protocol (IP) switches 125A1-125AK (for some non-zero natural number K). IP switches 125A1 and 125A2 are coupled to storage controllers (SCs) 130A1 and 130A2 via fiber channel connections, IP switches 125A3 and 125A4 are coupled to a general purpose (GP) server 145 via gigabit Ethernet, and IP switches 125A5 and 125A6 are coupled to a network (NET) 170 (e.g., a wide area network) via gigabit Ethernet. As shown, SCs 130A1 and 130A2 are coupled to serial attached SCSI (SAS) switches 135A1-135AJ (for some non-zero natural number J) which are coupled to JBODs (just a bunch of disks) 140A1-140AI (for some non-zero natural number I). GP server 145 includes services of archival storage 150 (e.g., tape storage), login 155 (e.g., user interface, remote user interface, etc.), code development 160 (e.g., compilers, development framework, debugger(s), profiler(s), simulator(s), etc.), and system administration 165.
In prior art supercomputing system 100, each of SCs 130A1 and 130A2 and I/O nodes 120A1-120AL is a computer system. Each of I/O nodes 120A1-120AL includes HPC host channel adapters (HCAs) to interface with two or more HPC switches 115A1-115AM and includes fiber channel network adapters and/or gigabit Ethernet network adapters to interface with two or more of IP switches 125A1-125AK. Each of SCs 130A1 and 130A2 includes fiber channel network adapters to interface with IP switches 125A1 and 125A2 and includes SAS controller adapters to interface with SAS switches 135A1-135AJ. In one or more implementations of prior art supercomputing system 100, there can be around one thousand five hundred (1500) compute nodes, one hundred twelve (112) I/O nodes, and thirty-two (32) storage controllers.